Tiled architecture is hot topic at chips conference

Tiled architecture has been high on the agenda at the 19th annual Hot Chips conference at Stanford University in Palo Alto, California.

Processor designers are promoting tiled architecture as the next generation of chip design, to take computing to a new level.

There is a limit to how many cores can be put on a chip, and tiled architecture addresses this problem.

The new parallel computing techniques use tiles laid out in a grid design. Each tile has a processor core which is connected by a router to an on-chip network which links all the cores together.

Instructions can move from tile to tile, backwards and forwards across the chip. Different instructions can also run parallel to each other simultaneously without having to wait for one another.

At the Hot Chips conference, Intel Corp. introduced its prototype 80-core processor, comprised of tiles laid out eight across and 10 down.

The prototype is just a research project at the moment, but is designed to give teraflop performance while running at under 100 watts.

Intel’s new chip features a sleep/wake function which switches off power to idle chips and wakes them when they are required.

This system is up to four times more efficient at reducing leakage than existing designs. It also reduces energy consumption in each tile’s router by up to seven times.

Tilera Corp also introduced a 64-core tiled processor at the conference, similar in design to Intel’s prototype. Tilera’s processor has tiles are arranged eight across and eight down.

It is an imbedded processor used in network routers and switches, and equipment for distributing high-definition video signals and is shipping now.

Tiled architecture has the advantage of producing less heat then traditional multicore systems, which present problems with cooling.

However a major disadvantage with parallel computing is that it is difficult to program software applications to run parallel instructions and will require a rethink of software design.